The present invention is related to circuits in which a field-effect transistor device controls power transfers from an alternating polarity electrical supply to a load means, particularly when such field-effect transistor devices are capable of being integrated into monolithic integrated circuits.
Various solid state devices have been used in circuits as the primary means for controlling power transfer from an alternating polarity electrical power supply to whatever kind of load means is of interest for use in the circuit. Noting the four above-referenced applications, one of the applications discloses such field-effect transistor devices as are suitable to be used as the primary means for controlling power transfers from an alternating polarity electrical power supply to such loads, and the other three applications show various circuit means for use in conjunction with such field-effect transistor devices to direct operation of these devices. As set out therein, the field-effect transistor device is a device which can provide symmetrical, bidirectional current conducting capability for use in alternating polarity power supply circuits. Particularly useful are devices which are effectively insulated-gate field-effect transistors (IGFET's), often metal-oxide-semiconductor field-effect transistors (MOSFET's), which have the further advantage of having the gate or control regions therein very well isolated from the remaining portions of the device including the channel region and the terminating regions at the ends of the channel region.
Such electrical isolation between the gate or control region, of an IGFET device and its remaining portions aids in providing a control circuit having as its purpose the directing of the operation of this transistor device. This isolation is particularly helpful when the control circuits and the transistor device are formed in a monolithic integrated circuit chip because a difficult control problem can arise when the power supplied to the integrated circuit is from an alternating polarity power supply. Such monolithic integrated circuit configurations must provide for the operation of the primary power transfer control IGFET device and the control of power transfers from the alternating polarity power supply to the load, while also providing for operation of other circuit components further provided in the monolithic integrated circuit chip.
As is well known, electronic component device theory shows that field-effect transistors are operated by controlling the voltage appearing between the gate thereof and the connection to that one of the two channel terminating regions therein which is effectively serving as a transistor source. Difficulties arise in those circuits using a field-effect transistor to control power transfers from an alternating polarity power supply to a load means because the two connections to the channel region of such a device serve alternately as source connections rather than one of them serving continually as the source connection.
FIG. 1 shows an abbreviated version of a circuit disclosed in the control circuit application referenced above having Ser. No. 973,215. This circuit uses what is effectively an enhancement mode, p-channel, IGFET, 10, for controlling power transfers from alternating polarity electrical power supply, 11, to a load means, 12, or alternatively, to a load means, 12', shown in dashed lines. Device 10 can be a device of the nature disclosed in the application referenced above having Ser. No. 24,840.
Field-effect transistor 10, being a p-channel IGFET, is provided in and on a substrate, 13, of a semiconductor material, typically silicon, which is doped, except in selected regions, to be of n-type conductivity. The channel connection or terminating regions, 15 and 16, which terminate the ends of the channel region (when a channel is induced) in transistor 10, are formed by diffusion or implantation of p-type conductivity impurities in the substrate material. Channel regions 15 and 16 can alternately serve as source and drain depending upon which is currently positive with respect to the other during operation. Parasitic diodes are formed in the structure of transistor 10 by the semiconductor pn junctions occurring between regions 15 and 16, on the one hand, and the remaining substrate material of transistor 10 on the other. These diodes are designated 17 and 18 in FIG. 1 and are shown in short dashed-line form to indicate that these are parasitics.
Also associated with these pn junctions but not shown are a number of other parasitic capacitances and parasitic resistances. All of these further parasitic components will have more or less of an effect on the operating behavior of transistor 10, and so in the behavior of the circuit in which transistor 10 is provided. The significance of the effects depends on the conditions existing in such a circuit and the values of the parasitic components. These parasitic components are shown in lumped form in the first three applications referenced above, but since dealing with these parasitic capacitances in the circuit is not a primary purpose of the various means disclosed in the present application, they have not been shown in FIG. 1 beyond showing of an effective lump parasitic capacitance, 24, between substrate 13 and gate 14 of transistor 10. Gate 14 is isolated from the substrate material of transistor 10 by an insulating layer.
At sufficiently low frequencies, the various parasitic capacitances indicated to be associated with transistor 10 of FIG. 1 will not be significant factors in the operation of the circuit of this figure. At higher frequencies, these capacitances must be taken into account in the circuit operation and, where detrimental, means must be provided for obviating the effects thereof. Such means are shown in the applications referenced above having Ser. Nos. 116,052 and 973,463 and are shown again, at least in part, in other figures of the present application. Also, the leakage resistances associated with transistor 10 are usually sufficiently large so that they will not be significant in the operation of this circuit.
Further, note that load means 12 could also have a reactance component thereto, but this has not been shown, and load means 12 will be described as being resistive for ease of understanding an exposition. This is also true of the alternative load means 12, that is, load means 12'. Load means 12' can be used in place of load means 12 with similar operating results in the circuit of FIG. 1 because of the symmetry inherent therein. For the following description, reference will be made only to load 12.
The primary control circuit portion for FIG. 1 is shown electrically connected between gate 4 and substrate 13 of transistor 10. This primary control circuit includes a constant polarity voltage source, 8, and a switch, 9. In the first position of switch 9, gate 14 of transistor 10 is directly electrically connected to substrate 13 of transistor 10, and constant polarity voltage source 8 is disconnected at the negative side thereof from the remaining portions of the circuit of FIG. 1. In these circumstances, supply 11 will alternately cause one of terminating regions 15 or 16 to be positive with respect to the other, and the terminating region then positive will be serving at that time as a source for transistor 10. Further, substrate 13 will not be more than a pn junction voltage drop less in voltage than whichever of terminating regions 15 and 16 is serving as the source because of the presence of parasitic diodes 17 and 18. As a result, the voltage between gate 14 and whichever of terminating regions 15 and 16 is serving as a source will be approximately the value of the voltage drop occurring across one of parasitic diodes 17 or 18 which will be substantially less than the threshold voltage of transistor 10. Device theory indicates that transistor 10 in these circumstances will be in the "off" condition.
In the other condition of switch 9, constant polarity voltage source 8 is in the circuit with its negative side connected to gate region 14 of transistor 10 and its positive side connected to substrate 13 of transistor 10. Effective capacitance 24 will then be charged by constant polarity voltage source 8 until the voltage thereacross is equal to the output voltage of source 8. With supply 11 again supplying an alternating voltage such that terminating regions 15 and 16 are alternately serving as the source for transistor 10, the source of transistor 10 will be no more than the voltage drop across one or the other of parasitic diodes 17 or 18 above the voltage at substrate 13. Hence, gate 14 will be negative with respect to whichever of the terminating regions is currently serving as a source. Assuming that the output voltage of source 8 is greater than the threshold voltage of transistor 10, device theory indicates that in these circumstances transistor 10 will then be switched into the "on" condition thereby permitting transfer of electrical power from alternating polarity power supply 11 to load means 12.
Since the setting of the position of switch 9 in practice will be entirely uncoordinated with the polarity and output voltage magnitude of alternating voltage supply 11, one can expect quite often that switch 9 will have its position changed to direct transistor 10 to switch from the "off" condition to the "on" condition at times when the voltage appearing between terminating regions 15 and 16 of transistor 10 is near its maximum value. Since capacitance 24 is of a quite small value, voltage source 8 will charge capacitance 24 extremely rapidly so that transistor 10 switches into the "on" condition quite abruptly thereby permitting very large currents to flow therethrough. Similarly, the position of switch 9 will often change to direct transistor 10 to switch from the "on" to the "off" condition at times when the current flow occurring through transistor 10 is very near its maximum value. Again, because capacitance 24 has a small value, capacitance 24 will rapidly discharge through switch 9 so that transistor 10 switches into the "off" condition quite abruptly leading to a sudden drop in the value of current flowing therethrough. Rates of change in current flow in these circumstances can be further affected by the presence of capacitive or inductive components in load 12.
As electromagnetic theory indicates, abrupt changes in current amplitude lead to electromagnetic radiation emanating from the circuit in which these changes occur. Such electromagnetic radiation can interfere with the performance and operation of other electronic systems sufficiently nearby. Further, abrupt changes in current amplitude can lead to electrical noise or transients being coupled to supply 11 and any other circuits or systems directly sharing supply 11. Thus, desirable operation of transistor 10 in FIG. 1 in switching from the "on" condition to the "off" condition, and vice versa, would be such as to prevent large current value changes at least in those situations where electromagnetic interference would be detrimental to the operation of nearby or electrically connected electronic systems.
As is well known, one method of reducing such electromagnetic interference is to prevent abrupt current level changes through switching primary power transfer controlling devices, such as transistor 10, from the "on" condition to the "off" condition, and vice versa, only when the voltage across such a device or the current through such a device is near its minimum value. Such switching can be difficult to achieve because electronic devices usually require at least some minimum voltage or current before they can respond to input commands. Further, providing such switching control in the same monolithic integrated circuit chip containing the primary power transfer control device is desirable but difficult to achieve when the chip is to be supplied alternating polarity electrical power.